A hole driver of a row address path for a semiconductor memory device is disclosed.
Generally, a semiconductor memory device has a row address path and a column address path. Blocks configuring the row address path and signals are represented as a symbol xe2x80x98Xxe2x80x99 and blocks configuring the column address path and signals are represented as a symbol xe2x80x98Yxe2x80x99.
The row address path includes a row control block, a row address strobe (RAS) signal generating block, an address latch block and a X-hole block.
FIG. 1 is a block diagram illustrating the row address path. The semiconductor memory device, i.e., specially, DRAM has a plurality of banks. Two banks BANK0 and BANK1 are shown in FIG. 1. Each bank has a plurality of sub blocks including a cell array. A sense amplifier S/A is disposed between each sub block. Each bank further has an X-hole including a row decoder X-DEC, a sense amplifier control unit, a wordline (W/L) enable control unit and an X-DEC control unit.
The semiconductor memory device has a hole driver or driver circuit for driving the X-hole, the hole driver including a bank control unit and a block address pre-decoder BAX. The bank control unit drives the sense amplifier control unit S/A and the W/L enable unit in the corresponding X-hole by receiving an output of a row address strobe signal generating block (not shown) and the block address pre-decoder drives the X-decoder control unit in corresponding X-hole by pre-decoding an address outputted from an address latch block (not shown) under control of the bank control unit.
In addition, when the output of the block address pre-decoder BAX is directly applied to the row decoder X-DEC, since drivability of the output thereof decreases due to a high load, a local address pre-decoder LAX is further included in the X-DEC control unit in the X-hole.
FIG. 2 is a block diagram illustrating the conventional hole driver in FIG. 1.
As shown, the hole driver includes a first bank control unit 22, a second bank control unit 24 and a block address pre-decoder 20. The first bank control unit 22 receives a row active pulse signal ractzp13x and a row precharge pulse signal rpcgzp13x outputted from the row address strobe signal generating block (not shown) and generates bank active pulse signals bxatvp16 and bxatvp22, bank precharge pulse signals bxpcgzp19 and bxpcgzp21, a wordline clear signal wlcz and a wordline enable control signal bsenz. The second bank control unit 24 receives the bank active pulse signal bxatvp22, the bank precharge pulse signal bxpcgzp21 and the wordline clear signal wlcz and generates a sense amplifier operation starting signal bsg. The block address pre-decoder 20, which includes a plurality of sub blocks BAX01, BAX23, BAX45, BAX678, BAX9A and BAXBC, pre-decodes the row address signals at-row less than 0:12 greater than  outputted from the row address latch block (not shown) in response to the bank active pulse signal bxatvp16 and the bank precharge pulse signal bxpcgzp19.
FIG. 3 is a circuit diagram illustrating the second bank control unit 24 in FIG. 2.
As shown, the second bank control unit 24 includes a first driver 30, a first inverter latch 31, a first delay 32, a second driver 33, a second inverter latch 34 and a pulse generator 35. The first driver 30 includes a PMOS transistor M1 and an NMOS transistor M2, whose gates receives the bank precharge pulse signal bxpcgzp21 and the bank active pulse signal, respectively. The first inverter latch 31 includes two inverters INV1 and INV2 connected to an output of the first driver 30 and the first delay 32 delays an output of the first inverter latch 31 for a predetermined time. The second driver 33 includes an NMOS transistor M7 whose gate receives the wordline clear signal wlcz, an NMOS transistor M8 whose gate receives an output signal of the first delay 32 and a PMOS transistor whose gate receives the wordline clear signal wlcz, wherein the transistors M9, M8 and M7 are connected in series between a power supply voltage xvdd and a ground voltage. The second inverter latch 34 includes an inverter INV5 connected to an output terminal of the second driver 33 and a PMOS transistor M10 for supplying a power supply voltage to the output terminal of the second driver 33 by receiving an output of the inverter INV5 to a gate thereof. The pulse generator 35 generates the sense amplifier operation starting signal bsg by receiving an output signal of the second inverter latch 34.
The first delay 32 includes a plurality of unit delays 36. The unit delay 36 includes a CMOS inverter INV3 having a resistance R connected a pull-down terminal thereof, MOS transistors M3, M4, M5 and M6 and switches S1, S2, S3 and S4 configuring a capacitor load and an inverter INV4.
The pulse generator 35 includes a second delay 37 for delaying an output signal of the second inverter latch 34 for a predetermined time, a NOR gate NOR1 receiving the output signal from the second inverter latch 34 and an output signal of the second delay 37, inverters INV6, INV7 and INV8 for buffering an output signal from the NOR gate NOR1 and outputting the sense amplifier operation starting signal bsg. The second delay 37 includes a plurality of unit delays, which are the same with those of the first delay 32.
The output signal of the second bank control unit 24, that is to say, the sense amplifier operation starting signal bsg is a flag signal for notifying when a driving operation of the sense amplifier is carried out after corresponding wordlines are completely enabled by inputting all row address signals to the X-hole and charge sharing operation for a bitline and a memory cell is completed.
FIG. 4 is a circuit diagram illustrating a first sub block BAX01 in the block address predecoder 20 (see FIG. 2).
As shown, the first sub block BAX01 receives the row address signal at_row less than 01 greater than  and outputs predecoded row address signals Bax01 less than 0:3 greater than . A circuit for generating the BAX01 less than 0 greater than  signal includes a driver 41, a latch 42 and a buffer 43. The driver 41 consists of a PMOS transistor M11 and NMOS transistors M12, M13 and M14 connected in series between a external voltage Vext and a ground voltage. The bank precharge pulse signal bxpcgzp19 is applied to a gate of the PMOS transistor M11. The bank active pulse signal bxatvp16, an address signal atz less than 0 greater than  and an address signal atz less than 1 greater than  are applied to gates of the NMOS transistors M12, M13 and M14, respectively. The address signal atz less than 0 greater than  is an inverted row address signal at_row less than 0 greater than  and the address signal atz less than 1 greater than  is an inverted row address signal at_row less than 1 greater than . Also, an address signal at less than 0 greater than  is an inverted address signal atz less than 0 greater than  and an address signal at less than 1 greater than is an inverted address signal atz less than 1 greater than  shown in FIG. 4.
The latch 42 consists of two inverters INV9 and INV10 and an output of the driver 41, which is a junction of the PMOS transistor M11 and the NMOS transistor M12, is connected to an input of the inverter INV10. The buffer 43 includes a plurality of inverters INV11 and INV12 for outputting the Bax01 signal.
Circuits for generating the predecoded Bax01 less than 1 greater than , Bax01 less than 2 greater than  and Bax01 less than 3 greater than signals are similar to the circuit for generating the Bax less than 0 greater than  signal. The differences are that the address signals at less than 0 greater than  and atz less than 1 greater than  are applied to generate the Bax01 less than 1 greater than  signal instead of the address signals atz less than 0 greater than  and atz less than 1 greater than  and the address signals atz less than 0 greater than  and at less than 1 greater than  are applied to generate the Bax01 less than 2 greater than  signal. Also, the address signals at less than 0 greater than and at less than 1 greater than  are applied to generate the Bax01 less than 3 greater than  signal.
If a row active command is applied from an external circuit, a row address strobe (RAS) signal and an address signal are inputted at the same time, so that the row active pulse signal ractzp13x signal is generated. The first bank control unit 22 of the hole driver generates the bank active pulse signal bxatvp16 by receiving the row active pulse signal ractzp13x. The block address predecoder 20 receives the bank active pulse signal bxatvp16 and latches corresponding row address signals until the precharge command is applied from the external circuit. Namely, the corresponding address signals have to be latched until the precharge command is inputted after a plurality of address lines Bax01 less than 0:3 greater than , Bax23 less than 0:3 greater than , Bax45 less than 0:3 greater than , Bax678 less than 0:3 greater than , Bax9A less than 0:3 greater than  and BaxBC less than 0:3 greater than  are enabled by activating corresponding bank.
Recently, in a memory device, specifically, e.g., a synchronous memory device, while one of banks is active, since another bank can be activated, the address lines connected to the block address predecoder have to be independently configured for each bank. Since the address lines connected to the block address predecoder is maintained in an active state by a precharge mode, a plurality of banks cannot share the block address predecoder.
Accordingly, a large area is occupied by the block address predecoder at each bank and the number of address lines is increased, so that there is a problem that the size of semiconductor memory chip must be increased which is contrary to the trends in this industry.
Therefore, a hole driver or driver circuit is disclosed capable of reducing the chip size of a semiconductor memory device by sharing the block address predecoder with a plurality of banks.
One disclosed hole driver or driver circuit comprises: a first bank control unit for generating a control signal for controlling a X-hole of a first bank in response to a row active signal and a precharge signal for the first bank; a second bank control unit for generating a control signal for controlling a X-hole of a second bank in response to a row active signal and a precharge signal for the second bank; a block address enable unit for generating a common block address enable signal in response to output signals of the first and the second bank control means; and a common block address predecoding unit for predecoding block address signal for each bank in response to the common block address enable signal.